Xilinx ML507 Hardware Designs

Table of Contents

Timesys Standard Reference Design

The Standard Reference Design is used with most Timesys starting points (unless otherwise noted). It includes a number of basic IP blocks for getting a board up and running.

Features

Peripheral IP Block Driver version
Processor ppc440_virtex5 1.00.a
Busses plb_v46 1.02.a
Memory ppc440mc_ddr2 1.02.a
xps_bram_if_cntlr 1.00.a
xps_mch_emc 1.01a
bram_blk 1.00.a
util_bus_split 1.00.a
JTAG jtagppc_cntlr 2.01.a
System Reset proc_sys_reset 2.00.a
DIP Switches xps_gpio 1.00a
8-Bit LEDs xps_gpio 1.00a
Position LEDs xps_gpio 1.00a
Push Buttons xps_gpio 1.00a
EEPROM xps_iic 2.00.a
Interrupt Controller xps_intc 1.00.a
Ethernet xps_ll_temac 1.01.b
xps_ll_fifo 1.00.b
P/S2 xps_ps2 1.00.a
 SystemACE xps_sysace 1.00.a
Serial xps_uart16550 2.00.a
Clock Generator clock_generator 2.01.a

Downloads

You can download the reference designs from the following locations:

Xilinx Reference Design

The Xilinx Reference Design is the hardware design provided by Xilinx for the ML507 board. We do not currently have a starting point compatible with this design.

Features

Peripheral IP Block Driver version
Processor ppc440_virtex5 1.01.a
Busses plb_v46 1.03.a
fcb_v20 1.00.a
Memory ppc440mc_ddr2 2.00.a
xps_bram_if_cntlr 1.00.a
xps_mch_emc 2.00a
bram_blk 1.00.a
util_bus_split 1.00.a
Floating Point apu_fpu_virtex5 1.01.a
JTAG jtagppc_cntlr 2.01.c
System Reset proc_sys_reset 2.00.a
DIP Switches xps_gpio 1.00a
8-Bit LEDs xps_gpio 1.00a
Position LEDs xps_gpio 1.00a
Push Buttons xps_gpio 1.00a
EEPROM xps_iic 2.00.a
Interrupt Controller xps_intc 1.00.a
Ethernet xps_ll_temac 1.01.b
SystemACE xps_sysace 1.00.a
Watchdog xps_timebase_wdt 1.00.b
Timer xps_timer 1.00.a
Serial xps_uart16550 2.00.b
Clock Generator clock_generator 2.01.a

Downloads

You can download the reference designs from the following locations: