Xilinx ML405 Hardware Designs

Timesys Standard Reference Design

The Standard Reference Design is used with most Timesys starting points (unless otherwise noted). It includes a number of basic IP blocks for getting a board up and running.


Peripheral IP Block Driver version
Processor ppc405_virtex4 2.01.a
Busses plb_v46 1.03.a
Memory mpmc 4.03.a
xps_bram_if_cntlr 1.00.a
bram_blk 1.00.a
util_bus_split 1.00.a
JTAG jtagppc_cntlr 2.01.c
System Reset proc_sys_reset 2.00.a
8-Bit LEDs xps_gpio 1.00a
Position LEDs xps_gpio 1.00a
Push Buttons xps_gpio 1.00a
EEPROM xps_iic 2.00.a
Interrupt Controller xps_intc 1.00.a
Ethernet xps_ll_temac 1.01.b
xps_ll_fifo 1.01.a
SystemACE xps_sysace 1.00.a
Serial xps_uart16550 2.00.b
Clock Generator clock_generator 2.01.a
MGT Wrapper mgt_protector 1.00.a


You can download the reference designs from the following locations: